1. Field of the Invention
The present invention relates to a method and system for providing fast Design for Testability (DFT) prototyping such as repetitive DFT implementation exploration before Automatic Test Pattern Generation (ATPG). More specifically, the present invention relates to a method and system for providing fast DFT prototyping to facilitate the application of DFT synthesis with traditional logic synthesis flow, including an STA (static timing analysis) enhanced DFT analysis approach with affinity-based scan replacement.
2. Description of the Related Art
As the complexity of today's chip design grows, the concept of Design for Testability (DFT) becomes more and more critical. Easy diagnosis of manufacturing defects of a complex System-on-chip (SoC) integrated circuit design relies on a good DFT methodology to be incorporated in the early chip design flow.
FIG. 1 is a block diagram representation of a typical IC design As shown, the SoC design 100 may include one or a plurality of third party Intellectual Property 101, 102, a clock generation block 103, analog blocks 104, memory blocks 105, core logic blocks 106, a plurality of I/O Pads 107. The Intellectual property 101, 102 may be, for example, a licensed proprietary design component. To incorporate DFT synthesis methodology in the design flow, test generation (including JTAG boundary scan blocks) and synthesizable core blocks may be used in the design flow. This is shown in FIG. 2. More specifically, FIG. 2 is a block diagram representation of a typical IC design with test generation and scan-style synthesizable core blocks. As can be seen from the Figure, the IC design representation shown in FIG. 2 includes a test generation block 201 as well as the other components of the IC design shown in FIG. 1.
As integrated circuits have become more complex and densely packed with gates, they have become progressively more difficult to test in order to ensure desired functionality. As a result, testability has become an increasingly more important and challenging goal of the integrated circuit design process. As discussed above, computer programs that aid in the design of testability circuitry for integrated circuits are often referred to as design for testability (DFT) processes. One approach to DFT, for example, is to take a netlist representing an integrated circuit design generated and to add and/or replace certain memory cells and associated circuitry of the netlist with special memory cells, called scan cells, designed to allow application of test vectors to certain portions of an integrated circuit produced according to the design.
Scan cells are interconnected to form scan chains. During test mode operation, scan test vectors in the form of a series of logical 1 and logical 0 test vector values are loaded into the scan cells of a scan chain. The circuit is caused to operate for a prescribed number of clock cycles using the test vectors as input. The results of the circuit operation can be captured in the form of logical 1 and logical 0 scan test results values. Scan test vectors and scan test results shall be referred to collectively as scan data. The same scan chain cells used to read in the test vectors can be used to capture the test results. The captured values are read out of the scan chain for observation and analysis. The results can be compared with expected results to determine whether the circuit operates as expected and to thereby determine whether defects are present.
FIGS. 3A–3B are flowcharts illustrating DFT prototyping and DFT synthesis, respectively, in a typical IC Design. Referring to FIG. 3A, typical DFT prototyping includes DFT synthesis step 310 whose results are verified to be satisfactory at step 320. In the case where the DFT synthesis provides satisfactory results at step 320, the routine proceeds to step 330 where Automatic Test Pattern Generation (ATPG) is applied. It should be noted that ATPG is a process to generate test patterns for a given netlist design to test the design's fault coverage. However, if the results at the DFT synthesis step 310 is determined to be not satisfactory at step 320, the routine performs the DFT synthesis step 310 again until the results are determined to be satisfactory at step 320.
More specifically, referring to FIG. 3B, the DFT synthesis step 310 typically includes the initial step of reading the design at step 311. Thereafter, the DFT constraints setting are determined at step 312. After determining the DFT constraints setting at step 312, DFT analysis is performed at step 313. Thereafter, at step 314, any DFT rule violation detected at DFT analysis step at 313 can be optionally fixed. Referring again to the Figure, at step 315, black box blocks like the memory blocks are bypassed, and thereafter, scan cell replacement is performed at step 316. As can be further seen from FIG. 3B, scan chain implementation and stitching is performed at step 317 after scan cell replacement at step 316, and thereafter, at step 318, final DFT reporting and netlist output is performed, before the routine proceeds to step 330 where ATPG is applied.
Referring back to FIG. 3B, more specifically, the DFT analysis step 313 includes various checking of DFT violations (such as for example, uncontrollable clock or asynchronous signals). Due to the nature of SoC system design, a traditional full chip DFT analysis requires a simulation-based analysis engine to account for the initial multi-cycle setup sequences of some building blocks, especially the test-generation blocks (e.g., block 201 in FIG. 2), and the clock generation blocks (e.g., block 103 in FIG. 2). Therefore, the process could be time consuming. There are also symbolic simulation approaches to speed up the simulation. However, symbolic-based approach typically cannot handle large SoC design due to common blowup in internal Binary Decision Diagram representation.
Referring back again to FIG. 3B, the scan cell replacement step 316 ensures that the replaced scan cells do not violate the original non-scan design's target requirements, such as power, timing and area requirements. This usually requires incremental optimization after scan cell replacement to ensure that the original specification is met. Incremental optimization, however, is another time consuming step. Furthermore, many DFT implementations are performed at the full-chip level, and often, IC designers are reluctant to run incremental optimization to avoid unexpected netlist change. Thus, the DFT synthesis tasks and ATPG in IC designs are often considered time consuming and difficult “back-end” design processes.
More specifically, scan cell replacement step 316 is an essential step in DFT synthesis 310 in IC design. The quality of scan cell replacement affects circuit area, timing and power consumption. In a typical scan implementation flow, an IC designer provides the tool an input netlist that is already logically and functionally optimized to satisfy a given set of constraints and timing signed off. The IC designer expects the non-scan sequential cells to be replaced as scan cells with minimum degradation to the circuit area, timing and power consumption. Any unnecessary optimization not only takes a long time, but also may change the circuit structure and characteristics including timing, circuit area, and power greatly.
U.S. Pat. No. 5,831,868 discloses scan cell replacement in which an ASCII function identification string based equivalence checking is used to decide which scan cell is used to replace the non-scan cell, emphasizing post scan chaining optimization to improve can implementation quality. U.S. Pat. No. 5,903,466 also discloses post scan chaining optimization step to improve scan implementation quality. However, post scan chaining optimization step may be too late in an IC design. Indeed, if the initial selection is bad, the optimization step can take a long time and completely disfigure a given circuit design such that no correlation exists between the original netlist and the final output netlist.